? semiconductor components industries, llc, 2002 april, 2002 rev. 4 1 publication order number: nbsg111/d nbsg111 product preview 2.5v/3.3vsige differential 1:10 clock/data driver with rsecl* outputs *reduced swing ecl the sg111 is a silicon germanium 1to10 differential clock/data driver. the device is functionally equivalent to the lvep111 device with much higher bandwidth and lower emi capabilities. inputs incorporate internal 50 termination resistors (input to vt pad) and accept necl (negative ecl), pecl (positive ecl), ttl, cmos, cml, or lvds. outputs are rsecl (reduced swing ecl), 400 mv. the q0:9/q0:9 outputs have a differential synchronous enable (en/en ) pin. the synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the internal flip flop is clocked on the falling edge of selected clock (clk0/clk0 or clk1/clk1 ), therefore all associated specification limits are referenced to the negative edge of the selected clock input. the v bb and v mm pins are internally generated voltage supplies available to this device only. the v bb is used for singleended necl or pecl inputs and the v mm pin is used for cmos inputs. for singleended input operation, the unused differential input is connected to v bb or v mm as a switching reference voltage. v bb or v mm may also rebias ac coupled inputs. when used, decouple v bb and v mm via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb and v mm outputs should be left open. ? maximum input clock frequency > 6 ghz typical ? 260 ps typical propagation delay ? 40 ps typical rise and fall times ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = 2.375 v to 3.465 v ? rsecl output level (400 mv peaktopeak output), differential output ? 50 internal input termination resistors ? compatible with existing 2.5 v/3.3 v lvep and ep devices ? v bb and v mm reference voltage output this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. sg111 = device code l = wafer lot y = year w = work week *for further details, refer to application note and8002/d fcbga49 ba suffix case 489a marking diagram* sg 111 device package shipping ordering information nbsg111ba 8x8 mm fcbga49 100 units/tray nbsg111bar2 8x8 mm fcbga49 500/tape & reel lyw board description sg111evb nbsg111ba evaluation board http://onsemi.com
nbsg111 http://onsemi.com 2 v ee v cc vcc nc q7 pin description pin sel*, sel ** vten, vten , vtsel, vtsel , vtclk0, vtclk0 , vtclk1, vtclk1 50 internal input termination resistors function clk0*, clk0 **, clk1*, clk1 ** ecl/ttl/cmos/cml/lvds compatible (clk) inputs q0:9, q0:9 rsecl data outputs v bb (ecl) reference voltage output * pin will default low when left open. ** pin will default to v cc /2 when left open. figure 1. pinout (top view) v ee q0 q0 v ee q1 en v mm q9 q9 q8 clk1 vtclk1 vten v cc vtclk1 clk1 a b c d 123 4 q8 q7 v ee 567 vtsel sel q6 vtsel sel q6 q1 q2 v ee q2 nc en vten v cc q3 vtclk0 q3 clk0 clk0 vtclk0 q4 vbb v ee q4 q5 q5 v ee e f g active clock select input en*, en ** output enable v mm nc negative supply (cmos) reference voltage output, (v cc v ee )/2 no connect positive supply
nbsg111 http://onsemi.com 3 (f6) v bb 0 1 (f4) clk0 (f5) clk0 (b4) clk1 (b3) clk1 (d6) sel q 0 (b1) q 0 (c1) q 1 (d1) q 1 (e1) q 2 (f1) q 2 (g2) q 3 (g3) q 3 (g4) q 4 (g5) q 4 (g6) q 5 (f7) q 5 (e7) q 6 (d7) q 6 (c7) q 7 (b7) q 7 (a6) q 8 (a5) q 8 (a4) q 9 (a3) q 9 (a2) (a1, a7, g1, g7) v ee (b5, d4, f3) v cc function table active input disabled outputs clk0, clk0 disabled outputs clk1, clk1 sel l l h h en l h l h (b2) v mm (e3) vten (e2) en (d3) vten (d2) en (c6) sel (c5) vtsel (e4) vtclk0 (e5) vtclk0 (c4) vtclk1 (c3) vtclk1 (d5) vtsel figure 2. logic diagram sync interfacing options interfacing options connections cml connect vtclk0, vtclk1, vten, vtsel and vtclk0 , vtclk1 , vten , vtsel to v cc lvds connect vtclk0, vtclk1, vten, vtsel and vtclk0 , vtclk1 , vten , vtsel together accoupled bias vtclk0, vtclk1, vten, vtsel and vtclk0 , vtclk1 , vten , vtsel inputs within common mode range (v ihcmr ) rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos see text on page 1. unused differential input switching voltage reference range is from v ee + 1125 mv to v cc 75 mv
nbsg111 http://onsemi.com 4 attributes characteristics value internal input pulldown resistor (clk0, clk0 , clk1, clk1 , sel, sel , en, en ) 75 k internal input pullup resistor (clk0 , clk1 , sel , en ) 36.5 k esd protection human body model machine model charged device model >2 kv >100 v tbd moisture sensitivity (note 1) level 3 flammability rating ul 94 v0 @ 0.125 in oxygen index 28 to 34 transistor count 457 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v 3.6 v v i positive input v ee = 0 v v i v cc 3.6 v v i positive in ut negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3 . 6 3.6 v v v inpp (inin) differential input voltage (|clk clk |) v cc v ee 2.8 v v cc v ee 2.8 v 2.8 |v cc v ee | v v i out output current continuous surge 25 50 ma ma i in input current through r t (50 resistor) static surge 45 80 ma ma i bb v bb sink/source 1 ma i mm v mm sink/source 1 ma ta operating temperature range 40 to +70 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) (note 3) 0 lfpm 500 lfpm 49 fcbga 49 fcbga 67 57 c/w c/w q jc thermal resistance (junction to case) 2s2p (note 3) 49 fcbga 2 to 4 c/w t sol wave solder < 15 sec. 225 c 2. maximum ratings are those values beyond which device damage may occur. 3. jedec standard 516, multilayer board 2s2p (2 signal, 2 power).
nbsg111 http://onsemi.com 5 dc characteristics, input with rspecl output v cc = 2.5 v; v ee = 0 v (note 4) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 90 ma v oh output high voltage (note 5) 1600 mv v outpp output pp voltage 400 mv v ih input high voltage (singleended) (notes 7 and 8) v thr + 75 v cc 1000* v cc v thr + 75 v cc 1000* v cc v thr + 75 v cc 1000* v cc mv v il input low voltage (singleended) (notes 7 and 9) v ih 2500 v cc 1400* v thr 75 v ih 2500 v cc 1400* v thr 75 v ih 2500 v cc 1400* v thr 75 mv v bb pecl output voltage reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mv v ihcmr input high voltage common mode range (differential) (note 6) 1.2 2.5 1.2 2.5 1.2 2.5 v v mm cmos output voltage reference (v cc v ee )/2 1100 1250 1400 1100 1250 1400 1100 1250 1400 mv r t internal termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 100 25 100 25 100 a dc characteristics, input with rspecl output v cc = 3.3 v; v ee = 0 v (note 10) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 90 ma v oh output high voltage (note 5) 2400 mv v outpp output pp voltage 400 mv v ih input high voltage (singleended) (notes 7 and 8) v thr + 75 v cc 1000* v cc v thr + 75 v cc 1000* v cc v thr + 75 v cc 1000* v cc mv v il input low voltage (singleended) (notes 7 and 9) v ih 2500 v cc 1400* v thr 75 v ih 2500 v cc 1400* v thr 75 v ih 2500 v cc 1400* v thr 75 mv v bb pecl output voltage reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mv v ihcmr input high voltage common mode range (differential) (note 6) 1.2 3.3 1.2 3.3 1.2 3.3 v v mm cmos output voltage reference (v cc v ee )/2 1500 1650 1800 1500 1650 1800 1500 1650 1800 mv r t internal termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 30 100 30 100 30 100 a i il input low current (@ v il ) 25 100 25 100 25 100 a note: sige circuits are designed to meet the dc specifications shown in the above tables after thermal equilibrium has been established. t he circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to 0.965 v. 5. all outputs loaded with 50 to v cc 1.5 volts. v oh /v ol measured at v ih /v il (typical). 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 7. v thr is the voltage applied to the complementary input, typically v bb or v mm . v thr(min) = v ihcmr + 75 mv. v thr(max) = v ihcmr 75 mv. 8. v ih cannot exceed v cc . 9. v il always v ee . 10. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to 0.165 v. *typicals used for testing purposes.
nbsg111 http://onsemi.com 6 dc characteristics, necl or rsnecl input with necl output v cc = 0 v; v ee = 3.465 v to 2.375 v (note 11) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 90 ma v oh output high voltage (note 12) 900 mv v outpp output pp voltage 400 mv v ih input high voltage (singleended) (notes 14 and 15) v thr + 75 v cc 1000* v cc v thr + 75 v cc 1000* v cc v thr + 75 v cc 1000* v cc mv v il input low voltage (singleended) (notes 14 and 16) v ih 2500 v cc 1400* v thr 75 v ih 2500 v cc 1400* v thr 75 v ih 2500 v cc 1400* v thr 75 mv v bb necl output voltage reference 1420 1360 1300 1420 1360 1300 1420 1360 1300 mv v ihcmr input high voltage common mode range (differential) (note 13) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v v mm cmos output voltage reference (note 17) v mmt 150 v mmt v mmt + 150 v mmt 150 v mmt v mmt + 150 v mmt 150 v mmt v mmt + 150 mv i ih input high current (@ v ih ) 30 100 30 100 30 100 m a i il input low current (@ v il ) 25 100 25 100 25 100 m a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. input and output parameters vary 1:1 with v cc . 12. all outputs loaded with 50 to v cc 1.5 volts. v oh /v ol measured at v ih /v il (typical). 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 14. v thr is the voltage applied to the complementary input, typically v bb or v mm . v thr(min) = v ihcmr + 75 mv. v thr(max) = v ihcmr 75 mv. 15. v ih cannot exceed v cc . 16. v il always v ee . 17. v mm typical = |v cc v ee | / 2 + v ee = v mmt . *typicals used for testing purposes. ac characteristics v cc = 0 v; v ee = 3.465 v to 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 3) (note 18) > 6 ghz t plh , t phl propagation delay to output differential 260 ps t skew duty cycle skew (note 19) withindevice skew (note 20) devicetodevice skew (note 21) < 10 < 15 < 85 ps t s setup time to clk (en to selected clk0:1) tbd ps t h hold time (en to selected clk0:1) tbd ps t jitter cycletocycle jitter (rms) (see figure 3) (note 18) < 2 ps v inpp input voltage swing/sensitivity (differential) (note 22) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times (20% 80%) q, q 40 ps 18. measured using a 500 mv source, 50% duty cycle clock source. all outputs loaded with 50 to v cc 1.5 v. 19. t skew = |t plh t phl | for a nominal 50% differential clock input waveform (figure 4). 20. withindevice skew is measured between outputs under identical transitions and conditions on any one device. 21. devicetodevice skew for identical transitions at identical v cc levels. 22. v inpp (max) cannot exceed v cc v ee (applicable only when v cc v ee 2600 mv).
nbsg111 http://onsemi.com 7 0 100 200 300 400 500 600 700 800 900 0 2000 4000 6000 8000 10000 12000 frequency (mhz) 1 2 3 4 5 6 7 8 figure 3. v out /jitter vs. frequency 9 tbd v outpp (mv) jitter out ps (rms) driver device receiver device qd 50 50 v tt q d figure 4. ac reference measurement clk /d clk/d q q t phl t plh v pp figure 5. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices) v tt = v cc 1.5 v
nbsg111 http://onsemi.com 8 package dimensions fcbga49 ba suffix plastic 8x8 mm (1.0 mm pitch) bga flip chip package case 489a issue a 0.15 terminal a1 corner z 0.12 c 0.20 c view zz e1 z a 0.15 c 0.08 c b 49 x feducial for pin a1 identification in this area 43 21 a e f g 49 x notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m-1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane c. 4. datum c (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. 6. 489a-01 obsolete, new standard 489a-02. m m 765 b c d e note 5 note 4 a2 a dim a min max millimeters a1 a2 0.91 ref b 0.40 0.60 d 8.00 bsc d1 6.00 bsc e 8.00 bsc e1 1.00 bsc e a b e d c 4 x c d1 e b note 3 detail a a1 seating plane detail a (rotated 90 c.w.) --- 1.40 6.00 bsc 0.3 0.5 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbsg111/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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